In the previous article, we studied combinational logic circuits, where the output depends only on the present input values. However, digital systems also need to remember information. A processor must retain states, counters must remember their current count, and registers must store binary data. This is where sequential logic circuits become essential. A sequential circuit differs from a combinational circuit because its output depends on both the present inputs and the previous state of the circuit. In this article, we will build the concept of sequential logic from the ground up, covering latches, flip-flops, SR, JK, D and T flip-flops, characteristic equations, excitation tables, race-around conditions, registers, shift registers, and counters.

1. What Is a Sequential Logic Circuit?

A sequential logic circuit is a digital circuit whose output depends on:

1. Present inputs
2. Previous state

Mathematically:$$\boxed{Y=F(X,Q)}$$

where:

• $X$ = present input
• $Q$ = present state
• $Y$ = output

The next state can be represented as:$$\boxed{Q^{+}=G(X,Q)}$$

where $Q^{+}$ represents the next state.

This ability to retain information is what gives sequential circuits memory.

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2. Combinational vs Sequential Logic

The distinction is fundamental.

Feature	Combinational Logic	Sequential Logic
Depends on present input	Yes	Yes
Depends on previous state	No	Yes
Memory	No	Yes
Feedback	Normally absent	Common
Clock	Not inherently required	Commonly used
Examples	Adder, MUX, Decoder	Flip-flop, Register, Counter

The easiest way to remember the difference is:$$\boxed{\text{Combinational = Present}}$$$$\boxed{\text{Sequential = Present + Past}}$$

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3. Basic Model of a Sequential Circuit

A sequential circuit can be viewed as two interacting parts:

                 ┌─────────────────┐
Inputs ─────────►│ Combinational   │──────► Outputs
                 │ Logic           │
                 └────────┬────────┘
                          │
                          ▼
                 ┌─────────────────┐
                 │ Memory Elements │
                 └────────┬────────┘
                          │
                          └──────► Present State

The memory elements store the circuit’s state.

The combinational logic determines what the next state should be.

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4. Why Do We Need Memory?

Consider a simple counter.

Suppose the circuit currently stores:$$0101$$

If the next clock pulse arrives, it should know that its current state is 5 and transition to:$$0110$$

Without memory, the circuit would have no knowledge of its previous state.

Therefore:$$\boxed{\text{Memory is essential for state-based digital systems}}$$

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5. Types of Sequential Circuits

Sequential circuits can broadly be classified as:

Sequential Logic
      │
      ├── Asynchronous Sequential Circuits
      │
      └── Synchronous Sequential Circuits

Asynchronous Sequential Logic

State changes can occur in response to input changes without relying on a common clock.

Synchronous Sequential Logic

State changes are coordinated by a clock signal.

Most modern digital systems rely heavily on synchronous sequential logic.

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6. What Is a Latch?

A latch is a basic memory element capable of storing one bit.

It has two stable states:$$0$$

and:$$1$$

Therefore, one latch can store:$$\boxed{1\text{ bit}}$$

A latch is generally level-sensitive.

That means its behavior can depend on whether an enable or control signal is active during a particular level.

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7. SR Latch

The SR latch is one of the simplest memory circuits.

SR stands for:

• S = Set
• R = Reset

Its purpose is to control the stored state.

For an active-high NOR-based SR latch:

S	R	Next State
0	0	Hold
0	1	Reset
1	0	Set
1	1	Invalid

The fundamental behavior is:$$S=1 \Rightarrow Q=1$$$$R=1 \Rightarrow Q=0$$

When:$$S=R=0$$

the previous state is retained.

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8. Why Is the SR Latch Important?

The SR latch introduces the fundamental concept of storage.

Unlike a combinational circuit:$$Q=f(S,R)$$

the latch can retain its previous value.

Conceptually:

Set
 ↓
Q becomes 1
 ↓
Inputs return inactive
 ↓
Q remains 1

That is memory.

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9. The Invalid State

For the active-high NOR SR latch:$$S=1,\quad R=1$$

is not a valid operating condition.

Both outputs would be forced toward the same state, violating the complementary relationship expected between $Q$ and $\overline Q$.

Therefore:$$\boxed{S=R=1\text{ is invalid for the NOR SR latch}}$$

This limitation motivates improved memory structures.

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10. D Latch

The D latch is designed to eliminate the invalid input combination associated with the basic SR latch.

D stands for Data.

It typically has:

• Data input $D$
• Enable input $E$
• Output $Q$

Its basic behavior is:

Enable $E$	D	Next $Q$
0	X	Hold
1	0	0
1	1	1

When:$$E=1$$

the latch is transparent:$$\boxed{Q=D}$$

When:$$E=0$$

the stored value is retained.

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11. Latch vs Flip-Flop

This distinction is extremely important.

Latch

A latch is generally level-sensitive.

Flip-flop

A flip-flop is generally edge-triggered.

A flip-flop normally changes state on a particular clock transition:

• Rising edge
• Falling edge

Therefore:$$\boxed{\text{Latch → Level sensitive}}$$$$\boxed{\text{Flip-Flop → Edge triggered}}$$

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12. What Is a Flip-Flop?

A flip-flop is a bistable memory element capable of storing one bit.

It has two stable states:$$Q=0$$

and:$$Q=1$$

Flip-flops are fundamental building blocks of:

• Registers
• Counters
• State machines
• Memory structures
• Processor datapaths
• Digital control systems

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13. Clock Signal

Synchronous sequential circuits commonly use a clock.

A clock is a periodic digital signal:

      ┌───┐     ┌───┐
──────┘   └─────┘   └─────

The clock provides a reference point for state transitions.

Two common triggering mechanisms are:

Positive-edge triggering

State changes on:$$\boxed{\uparrow}$$

the rising edge.

Negative-edge triggering

State changes on:$$\boxed{\downarrow}$$

the falling edge.

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14. SR Flip-Flop

The SR flip-flop is the clock-controlled form of the SR memory concept.

Inputs:$$S,\ R$$

Output:$$Q$$

For the active-high form:

S	R	$Q^{+}$
0	0	Q
0	1	0
1	0	1
1	1	Invalid

The corresponding characteristic equation is commonly written as:$$\boxed{Q^{+}=S+\overline RQ}$$

with the invalid input condition excluded.

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15. D Flip-Flop

The D flip-flop is one of the most widely used flip-flops in digital systems.

It has:

• D input
• Clock
• Q output

Its defining relationship is:$$\boxed{Q^{+}=D}$$

At the active clock edge, the value at $D$ is transferred to $Q$.

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16. D Flip-Flop Truth Table

D	$Q^{+}$
0	0
1	1

Therefore:$$\boxed{Q^{+}=D}$$

This simplicity makes D flip-flops extremely useful for data storage.

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17. Applications of D Flip-Flops

D flip-flops are commonly used in:

• Registers
• Shift registers
• Pipeline stages
• Data storage
• Synchronizers
• State machines
• Digital signal processing hardware

A chain of D flip-flops can store multiple bits.

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18. JK Flip-Flop

The JK flip-flop improves upon the SR flip-flop by eliminating the invalid input condition.

Inputs:$$J,\ K$$

Its characteristic behavior is:

J	K	$Q^{+}$
0	0	Q
0	1	0
1	0	1
1	1	$\overline Q$

Therefore, when:$$J=K=1$$

the output toggles.

Its characteristic equation is:$$\boxed{Q^{+}=J\overline Q+\overline KQ}$$

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19. Why Is the JK Flip-Flop Important?

The JK flip-flop can perform four fundamental operations:

J K = 00 → Hold
J K = 01 → Reset
J K = 10 → Set
J K = 11 → Toggle

The toggle operation makes JK flip-flops especially useful in counter design.

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20. T Flip-Flop

The T flip-flop is designed primarily for toggling.

T stands for:$$\boxed{\text{Toggle}}$$

Its behavior is:

T	$Q^{+}$
0	Q
1	$\overline Q$

Therefore:$$\boxed{Q^{+}=T\oplus Q}$$

When:$$T=0$$

the flip-flop holds its state.

When:$$T=1$$

the output toggles.

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21. Characteristic Equations

Characteristic equations describe the next state of a flip-flop in terms of its inputs and present state.

SR

$$\boxed{Q^{+}=S+\overline RQ}$$

with the invalid condition excluded.

D

$$\boxed{Q^{+}=D}$$

JK

$$\boxed{Q^{+}=J\overline Q+\overline KQ}$$

T

$$\boxed{Q^{+}=T\oplus Q}$$

These equations are extremely important for sequential-circuit analysis and design.

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22. Characteristic Table

A convenient comparison:

Flip-Flop	Input	Next-State Relationship
SR	S, R	Set / Reset / Hold
D	D	$Q^{+}=D$
JK	J, K	Hold / Reset / Set / Toggle
T	T	Hold / Toggle

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23. Excitation Table

Characteristic tables answer:

Given the input, what will the next state be?

An excitation table asks the reverse:

Given the present and desired next state, what input is required?

This is particularly useful when designing sequential circuits.

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24. D Flip-Flop Excitation Table

Because:$$Q^{+}=D$$

we simply require:

Q	$Q^{+}$	D
0	0	0
0	1	1
1	0	0
1	1	1

Therefore:$$\boxed{D=Q^{+}}$$

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25. T Flip-Flop Excitation Table

Q	$Q^{+}$	T
0	0	0
0	1	1
1	0	1
1	1	0

Therefore:$$\boxed{T=Q\oplus Q^{+}}$$

A T input of 1 is required whenever the state must change.

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26. JK Flip-Flop Excitation Table

Q	$Q^{+}$	J	K
0	0	0	X
0	1	1	X
1	0	X	1
1	1	X	0

Here:$$X=\text{Don’t Care}$$

The don’t-care values provide design flexibility during logic minimization.

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27. Race-Around Condition

One important issue associated with the level-triggered JK flip-flop is the race-around condition.

When:$$J=K=1$$

the output should toggle.

However, if the clock pulse remains active long enough, the output may toggle repeatedly during the same clock pulse.

Conceptually:

Q
0 → 1 → 0 → 1 → 0 ...

This makes the final state unpredictable.

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28. How Is Race-Around Prevented?

Common solutions include:

1. Edge-triggered flip-flops

The state changes only at a clock edge.

2. Master-slave configuration

Two stages operate sequentially to prevent repeated toggling during one clock pulse.

3. Properly controlled clock pulse width

Reducing the active clock duration can prevent unwanted multiple transitions.

The fundamental goal is:$$\boxed{\text{Allow only one intended state transition per clock event}}$$

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29. Registers

A register is a group of flip-flops used to store multiple bits.

For example, a 4-bit register requires:$$\boxed{4\text{ flip-flops}}$$

A 32-bit register requires:$$\boxed{32\text{ storage elements}}$$

Conceptually:

Bit 3 → FF
Bit 2 → FF
Bit 1 → FF
Bit 0 → FF

Together, they store a binary word.

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30. Types of Registers

Important types include:

• Parallel-in Parallel-out (PIPO)
• Serial-in Serial-out (SISO)
• Serial-in Parallel-out (SIPO)
• Parallel-in Serial-out (PISO)

These configurations determine how data enters and leaves the register.

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31. Shift Registers

A shift register moves stored data from one flip-flop to another with each clock event.

For example:

Q3 ← Q2 ← Q1 ← Q0

After a clock pulse, the stored data shifts by one position.

Shift registers are useful for:

• Serial communication
• Data conversion
• Temporary storage
• Delay elements
• Digital signal processing

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32. Serial-In Serial-Out Register

In a SISO register:$$\boxed{\text{Serial Input → Serial Output}}$$

Data enters one bit at a time and leaves one bit at a time.

For a 4-bit register:

Serial In
    ↓
[FF] → [FF] → [FF] → [FF]
                         ↓
                    Serial Out

Each clock pulse moves the data one stage forward.

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33. Serial-In Parallel-Out

A SIPO register accepts data serially but provides multiple outputs.

Serial Input
     ↓
[FF] → [FF] → [FF] → [FF]
       ↓      ↓      ↓      ↓
      Q3     Q2     Q1     Q0

This is useful when serial data must be converted into a parallel word.

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34. Parallel-In Serial-Out

A PISO register accepts multiple bits simultaneously and then shifts them out sequentially.

It is useful when:$$\boxed{\text{Parallel data → Serial transmission}}$$

is required.

This principle is used in various data-transfer architectures.

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35. Counters

A counter is a sequential circuit that moves through a predetermined sequence of states in response to clock pulses.

For a simple binary up-counter:$$0000$$$$0001$$$$0010$$$$0011$$$$0100$$

and so on.

Therefore, a counter is essentially a controlled state machine.

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36. Asynchronous Counter

An asynchronous counter, also called a ripple counter, does not clock all flip-flops simultaneously from the same clock source.

Instead, the output of one stage influences the clocking of the next stage.

Conceptually:

Clock
  ↓
FF0 → FF1 → FF2 → FF3

The state transition ripples through the stages.

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37. Disadvantage of Ripple Counters

Because the state transitions propagate through multiple stages, there is cumulative propagation delay.

For a larger counter, this can become significant.

Therefore:$$\boxed{\text{Ripple counters are simple but slower}}$$

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38. Synchronous Counter

In a synchronous counter, all flip-flops receive the same clock signal.

             ┌→ FF0
Clock ───────┼→ FF1
             ├→ FF2
             └→ FF3

The required state transitions are controlled through combinational logic.

Because the flip-flops respond to the same clock edge, synchronous counters can operate at higher speeds than ripple counters for comparable implementations.

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39. Asynchronous vs Synchronous Counters

Feature	Asynchronous Counter	Synchronous Counter
Clocking	Cascaded	Common clock
Propagation delay	Accumulates	Lower state-transition skew
Design	Simpler	More logic required
Speed	Lower	Higher
Typical use	Simple counting	High-speed digital systems

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40. Modulus of a Counter

The modulus, or MOD number, is the number of distinct states through which a counter cycles.

An $n$-bit binary counter can have up to:$$\boxed{2^n}$$

states.

For example, a 3-bit binary counter has:$$2^3=8$$

states.

Therefore:$$\boxed{\text{3-bit counter → MOD-8}}$$

A 4-bit binary counter has:$$2^4=16$$

states.

Therefore:$$\boxed{\text{4-bit counter → MOD-16}}$$

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41. MOD-N Counter

A counter does not necessarily have to use all $2^n$ possible states.

For example, a MOD-10 counter cycles through:$$0\rightarrow1\rightarrow2\rightarrow\cdots\rightarrow9\rightarrow0$$

It therefore has:$$\boxed{10\text{ states}}$$

Such counters are commonly used in decimal counting and timing applications.

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42. State Diagram

Sequential circuits can be represented using a state diagram.

A state diagram consists of:

• States
• Transitions
• Inputs
• Outputs

For a simple two-state system:

       input = 1
   ┌──────────────┐
   │              ▼
 [0] ───────────► [1]
   ▲              │
   └──────────────┘
       input = 1

The diagram provides a visual representation of how the circuit moves between states.

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43. State Table

A state table provides the same type of information in tabular form.

Typical columns include:

Present State	Input	Next State	Output
$Q$	X	$Q^{+}$	Y

State tables are particularly useful when designing finite-state machines.

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44. Moore and Mealy Machines

Sequential systems are often modeled using two common finite-state-machine architectures.

Moore Machine

Output depends only on the present state:$$\boxed{Y=F(Q)}$$

Mealy Machine

Output depends on present state and input:$$\boxed{Y=F(Q,X)}$$

This distinction becomes important in control systems and digital design.

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45. Timing Parameters

Real flip-flops have important timing requirements.

Setup Time

The input must remain stable for a minimum period before the active clock edge.

Hold Time

The input must remain stable for a minimum period after the active clock edge.

Clock-to-Q Delay

The time between the active clock edge and the corresponding output transition at $Q$.

These parameters are critical in synchronous digital-system design.

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46. Metastability

If timing requirements are violated, a flip-flop can enter a temporary state where its output is neither a clean logic 0 nor a clean logic 1.

This condition is called metastability.

It is particularly important when transferring signals between different clock domains.

Common mitigation techniques include:

• Synchronizer flip-flop chains
• Proper clock-domain-crossing design
• Timing analysis

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47. Complete Sequential Logic Flow

The progression can now be visualized as:

Sequential Logic
       ↓
Memory
       ↓
Latches
       ↓
Flip-Flops
       ↓
Registers
       ↓
Counters
       ↓
State Machines
       ↓
Digital Systems

This is one of the most important conceptual progressions in digital electronics.

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48. Key Equations

D Flip-Flop

$$\boxed{Q^{+}=D}$$

JK Flip-Flop

$$\boxed{Q^{+}=J\overline Q+\overline KQ}$$

T Flip-Flop

$$\boxed{Q^{+}=T\oplus Q}$$

T Excitation

$$\boxed{T=Q\oplus Q^{+}}$$

SR Flip-Flop

$$\boxed{Q^{+}=S+\overline RQ}$$

with the invalid input condition excluded.

Number of states for $n$ storage bits

$$\boxed{N=2^n}$$

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49. Common Mistakes

Mistake 1 — Calling a latch edge-triggered

A latch is generally:$$\boxed{\text{Level-sensitive}}$$

A flip-flop is generally:$$\boxed{\text{Edge-triggered}}$$

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Mistake 2 — Confusing present and next state

$$Q=\text{Present State}$$$$Q^{+}=\text{Next State}$$

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Mistake 3 — Forgetting the JK toggle condition

When:$$J=K=1$$

the JK flip-flop toggles:$$\boxed{Q^{+}=\overline Q}$$

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Mistake 4 — Assuming every counter is MOD-$2^n$

A basic $n$-bit binary counter has $2^n$ states, but counters can be designed with other moduli.

For example:$$\boxed{\text{MOD-10}}$$

uses ten states rather than sixteen.

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Mistake 5 — Ignoring setup and hold time

Real synchronous systems cannot change data arbitrarily close to a clock edge.

Timing constraints are fundamental to reliable digital design.

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50. Quick Revision Table

Topic	Key Point
Sequential Logic	Output depends on present input + state
Latch	Level-sensitive memory
Flip-Flop	Edge-triggered memory
SR	Set / Reset
D	Data storage
JK	Set / Reset / Toggle
T	Toggle
Register	Stores multiple bits
Shift Register	Moves data between stages
Counter	Sequentially changes states
Ripple Counter	Asynchronous
Synchronous Counter	Common clock
State Diagram	Graphical state representation
State Table	Tabular state representation
Moore	Output depends on state
Mealy	Output depends on state + input

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Conclusion

Sequential logic is the point where digital electronics moves beyond simple input-to-output processing and introduces memory, state, timing, and controlled state transitions. Latches provide basic storage, while flip-flops provide reliable clock-controlled storage. These flip-flops can then be combined to construct registers, shift registers, counters, and finite-state machines.

The central concept can be summarized as:$$\boxed{ \text{Combinational Logic} + \text{Memory} = \text{Sequential Logic} }$$

The progression of the Digital Electronics series is now:$$\boxed{ \text{Number Systems} \rightarrow \text{Logic Gates} \rightarrow \text{Boolean Algebra} \rightarrow \text{K-Maps} \rightarrow \text{Combinational Logic} \rightarrow \text{Sequential Logic} }$$

The next step is to go deeper into flip-flops and their timing behavior, followed by registers, shift registers, counters, and finite-state-machine design.